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W631GG6KB
The use of Self-Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3
SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh
Mode.
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
CK#
CK
CKE
t IS
t CPDED
t CKSRE
t CKSRX
VALID
VALID
t CKESR
t IS
ODT
ODTL
VALID
Command
NOP
SRE
NOP
SRX
NOP *1
VALID *2
VALID *3
Address
t RP
Enter Self Refresh
Exit Self Refresh
VALID
t XS
t XSDLL
TIME BREAK
VALID
DON'T CARE
Notes:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
Figure 58 – Self-Refresh Entry/Exit Timing
Publication Release Date: Dec. 09, 2013
Revision A05
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